As with any complex software, MCU T5.3.19 has its own list of errata as of Q1 2026:
Manufacturer has committed to a minor patch (T5.3.20) by Q3 2026 to resolve the I2C issue.
Prior to the rollout of MCU T5.3.19, devices running T5.2.x or earlier were susceptible to a voltage glitching attack combined with a cache timing analysis. The key security enhancements include: mcu t5.3.19
DMA channel completion interrupts now use a priority ceiling protocol when sharing the same interrupt line with a higher-priority ADC conversion. Prevents starvation where DMA completion was perpetually deferred.
A low-overhead counter (2 DWT cycles per read) has been added to the scheduler. Enable with #define CONFIG_TASK_CYCLE_PROFILE 1. As with any complex software, MCU T5
Example output (RTT):
I am Attila Fodor (Kevin for friends, but it's a long story), and I produce music since 1999 under the alias of
Task | MinCyc | MaxCyc | AvgCyc | %CPU
CAN_Tx | 412 | 5230 | 892 | 14.2
PID_Control | 98 | 128 | 105 | 31.7
USB_Heartbeat | 56 | 1950* | 312 | 3.1
(*max spike due to USB SOF interrupt)
The "MCU" in this context is a laboratory designation often used to denote the specific catalog or repository origin (e.g., Master Culture Unit or a specific university/research lab code).