| Feature | PCIe 5.0 (Gen 5) | PCIe 6.0 (Gen 6) | | :--- | :--- | :--- | | Data Rate | 32 GT/s | 64 GT/s | | Bandwidth (x16) | ~64 GB/s (approx. 128 GB/s bi-directional) | ~128 GB/s (approx. 256 GB/s bi-directional) | | Encoding Scheme | 128b/130b (NRZ) | PAM4 (with FEC) | | Packet Format | Variable size (TLP/ DLLP) | Fixed-size FLIT (256 bytes) | | Power Management | L1 substates | L0p (Per-lane power down) | | Target Latency | Standard | Sub-Ins latency (via FLIT) |
Note: Bandwidth calculations are raw theoretical maximums. The spec PDF details the actual payload throughput accounting for FEC overhead. pci express base specification revision 60 pdf
A common question: Will my PCIe 6.0 slot work with my old PCIe 3.0 sound card? | Feature | PCIe 5
Yes, but with nuances. The PCIe specification has always prided itself on backward compatibility. A PCIe 6.0 link will fall back to the highest common supported speed. A common question: Will my PCIe 6
However, because PAM4 vs. NRZ signaling is fundamentally different, the Link Training and Status State Machine (LTSSM) has been expanded. The PCI Express Base Specification Revision 6.0 PDF introduces new states for:
Anyone speccing out an AI cluster or High-Performance Computing (HPC) solution needs to understand the implications of L0p for power budgeting and FLIT for CXL 3.0 coherency.