This is often the core of the XUP DSP Primer.
A significant portion of the updated Primer addresses Vivado HLS (now part of Vitis). Traditional RTL design (Verilog/VHDL) is precise but slow to iterate. HLS allows you to write C/C++ and compile it to RTL.
The Primer’s Stance: "Understand RTL first, use HLS second."
The primer includes labs where you write a C++ FIR filter, add pragmas like #pragma HLS PIPELINE or #pragma HLS UNROLL, and watch the tool generate a parallel datapath. Xilinx University Program - DSP for FPGA Primer...
Key takeaway from HLS chapters: You must still understand DSP architecture. If you write a for loop and don't unroll it, HLS will synthesize a sequential, slow circuit. If you do unroll it, you get a parallel FIR. The Primer teaches you how to "think in circuits" even when writing C++.
Here’s the hook that grabs engineering students:
In a microprocessor, you write code that executes step-by-step. In an FPGA, you create the hardware—thousands of multiply-accumulate units running in parallel, each dedicated to one job. This is often the core of the XUP DSP Primer
Example:
A typical 32-tap FIR filter on a 200 MHz ARM Cortex-M takes ~32 cycles per sample. On an FPGA using the XUP primer’s systolic architecture, it takes 1 clock cycle for all 32 taps. That’s a 32x speedup—without increasing clock frequency.
The primer shows you how to design that systolic array, retime it, and verify it on a real Artix-7 or Zynq board.
Undergraduate students (junior/senior) or early grad students in EE/CS with basic signals & systems and digital logic knowledge. Lab Exercise: Building a simple signal generator or
The Fast Fourier Transform is central to OFDM, spectrum analysis, and radar. The XUP primer covers:
Students use the Xilinx FFT LogiCORE IP, configuring it for pipeline streaming versus burst I/O.
For communications engineers, the mixer + filter chain is critical. Here, the primer integrates:
Before diving into the DSP specifics, it is crucial to understand the host ecosystem. The Xilinx University Program is a global initiative that provides academic institutions with:
The goal of XUP is to ensure that graduating engineers are not merely familiar with FPGA theory but possess practical, job-ready skills. The DSP for FPGA Primer is the flagship document for teaching how to implement digital filters, transforms, and modulators in reconfigurable logic.